1. Field of the Invention
This invention relates to a non-volatile semiconductor storage apparatus and a process of producing the same, and more particularly to an electrically erasable non-volatile semiconductor storage apparatus which has a three-dimensional structure and a process of producing the same.
2. Description of the Related Art
In recent years, as an increase in storage capacity and degree of integration of semiconductor storage apparatus proceeds, attention is paid to a non-volatile semiconductor storage apparatus having a memory cell of a three-dimensional structure as a semiconductor storage apparatus in which cell arrays can be arranged with a high density. An exemplary one of such non-volatile semiconductor storage apparatus is disclosed in "Performance of the 3-D Sidewall Flash EPROM Cell", IEEE IEDM 93.2.1, 1993.
The structure and a process of production of an EEPROM flash memory are described below with reference to FIGS. 8 and 9. FIG. 8 is a plan view of the conventional three-dimensional EEPROM flash memory, and FIG. 9 is a sectional view taken along line 9'-9" in FIG. 8. As seen from FIGS. 8 and 9, a plurality of p-type silicon pillars 12 formed by etching are arranged in a matrix on a silicon substrate 1. A polycrystalline silicon film 5 serving as a floating gate is formed around each of the silicon pillars 12 with a gate oxide film 4 interposed therebetween.
A drain region 6 is formed at the top of each of the silicon pillars 12, and a source region 7 is formed continuously on the surface of the silicon substrate 1 around the individual silicon pillars 12. A second polycrystalline silicon film 9 serving as a control gate is formed around each of the polycrystalline silicon films 5 serving as floating gates with a layered insulation film 8 interposed therebetween. The second polycrystalline silicon films 9 are formed continuously in the direction of a row to construct word lines. The surfaces of the second polycrystalline silicon films 9 are covered with an interlayer insulation film 10. The drain regions 6 formed on the silicon pillars 12 are connected commonly for the individual columns to bit lines 11 which extend in the direction of a column.
The EEPROM is formed in the following manner.
1 An etching mask of a silicon oxide film is formed on a p-type silicon substrate 1, and the silicon substrate 1 is etched by RIE (Reactive Ion Etching) to form silicon pillars 12.
2 A gate oxide film 4 is formed by thermal oxidation, and deposition and etching back of polycrystalline silicon are performed to form a polycrystalline silicon film 5 on the side faces of each of the silicon pillars 12.
3 Ion implantation of arsenic is performed to form drain regions 6 and a source region 7.
4 A layered insulation film 8 is formed over the entire area, and deposition and etching back of polycrystalline silicon are performed to form second polycrystalline silicon films 9 which cover over the circumferences of the floating gates and fill up the gaps between the silicon pillars 12 in the direction of a row.
5 An interlayer insulation film 10 is formed.
6 The interlayer insulation film 10 on the silicon pillars 12 is removed, and deposition and patterning of a metal film are performed to form bit lines 11. By the process, a three-dimensional EEPROM flash memory is produced.
With the conventional process of production described above, since silicon pillars are formed by etching of a substrate, it is difficult to form the silicon pillars with an equal height. While the height is an important parameter which determines the channel length of a memory cell transistor, since silicon pillars of memory cell transistors produced by the conventional process exhibit a dispersion in height, they exhibit a large dispersion in threshold value V.sub.T upon erasure and writing of data, resulting in a drawback that the memory cell exhibits a high degree of possibility in malfunction (error in read-out).
Further, in the memory cell described above, upon erasure of data, a high voltage is applied to the source region 7 to remove electrons from the floating gates (polycrystalline silicon film 5). In this instance, the gate oxide film 4 is used as a tunnel oxide film. Since the gate oxide film is obtained by thermal oxidation of the silicon substrate 1 which has been damaged by etching performed for the formation of the silicon pillars, the gate oxide film reflects some of defects of the silicon substrate 1 and cannot be formed as a film of a high quality. Consequently, there is a problem in that the memory cell is Inferior in write repeat characteristics and erasure characteristics.
Also in a non-volatile semiconductor storage apparatus and a process of production of the same disclosed in Japanese Patent Laid-Open Application No. Heisei 6-112503, upon formation of a tunnel oxide film, a groove is formed on a silicon substrate by etching, and a floating gate, an interlayer insulation film, a control gate and so forth are formed in the groove. In this instance, since the tunnel oxide film is formed by thermal oxidation of the bottom and the side walls of the groove of the silicon substrate which has been damaged by the preceding etching, there is a problem in that the tunnel oxide film has a degraded film quality, which deteriorates the reliability of the memory cell.